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MC74ACT564 Octal D-Type Flip-Flop with 3-State Outputs
The MC74ACT564 is a high-speed, low power octal flip-flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock (CP) transition. The MC74ACT564 device is functionally indentical to the MC74ACT574, but with inverted outputs.
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* Inputs and Outputs on the Opposite Sides of the Package Allowing * * * * * *
Easy Interface with Microprocessors Useful as Input or Output Port for Microprocessor Functionally Indentical to the MC74ACT574 but with Inverted Outputs 3-State Outputs for Bus-Oriented Applications Outputs Source/Sink 24 mA TTL Compatible Inputs Pb-Free Packages are Available*
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PDIP-20 N SUFFIX CASE 738
SOIC-20W DW SUFFIX CASE 751D 1
VCC 20
O0 19
O1 18
O2 17
O3 16
O4 15
O5 14
O6 13
O7 12
CP 11
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet.
DEVICE MARKING INFORMATION
1 OE 2 D0 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 GND
See general marking information in the device marking section on page 5 of this data sheet.
Figure 1. Pinout: 20-Lead Packages Conductors
(Top View) D0 D1 D2 D3 D4 D5 D6 D7
PIN ASSIGNMENT
PIN D0-D7 CP OE O0-O7 FUNCTION Data Inputs Clock Pulse Input 3-State Output Enable Input 3-State Outputs
CP OE O0 O1 O2 O3 O4 O5 O6 O7
Figure 2. Logic Symbol
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
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December, 2006 - Rev. 3
Publication Order Number: MC74ACT564/D
MC74ACT564
D0 CP C Q D C Q
D1
D2
D3
D4
D5
D6
D7
D
C Q
D
C Q
D
C Q
D
C Q
D
C Q
D
C Q
D
OE O0 O1 O2 O3 O4 O5 O6 O7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
FUNCTION TABLE
Inputs OE H H H H L L L L H L X Z = = = = = NC = H H CP H H D L H L H L H L H Internal Q NC NC H L H L NC NC Outputs Function O Z Z Z Z H L NC NC Hold Hold Load Load Data Available Data Available No Change in Data No Change in Data
HIGH Voltage Level LOW Voltage Level Immaterial High Impedance LOW-to-HIGH Transition No Change
FUNCTIONAL DESCRIPTION The MC74ACT564 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-state complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
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MC74ACT564
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink/Source Current DC Supply Current per Output Pin DC Ground Current per Output Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating Oxygen Index: 30% - 35% PDIP SOIC PDIP SOIC (Note 1) Parameter Value *0.5 to )7.0 *0.5 v VI v VCC )0.5 *0.5 v VO v VCC )0.5 $20 $50 $50 $50 $50 *65 to )150 260 )150 67 96 750 500 Level 1 UL 94-V0 @ 0.125 in > 2000 > 200 > 1000 $100 V Unit V V V mA mA mA mA mA _C _C _C _C/W mW
ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Latchup Performance Above VCC and Below GND at 85_C (Note 5)
ILatchup
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf TJ IOH IOL Parameter DC Input Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Note 7) Junction Temperature (PDIP) Output Current - High Output Current - Low VCC = 4.5 V VCC = 5.5 V Min 4.5 0 -40 0 0 25 10 8.0 Typ Max 5.5 VCC +85 10 8.0 140 -24 24 Unit V V C ns/V C mA mA
6. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level. 7. Vin from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.
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MC74ACT564
DC CHARACTERISTICS
TA = +255C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.001 0.001 0.1 0.1 0.36 0.36 0.1 0.6 0.5 TA = -405C to +855C Unit V V V V V V V V V V V V mA mA mA Conditions VOUT = 0.1 V or VCC - 0.1 V VOUT = 0.1 V or VCC - 0.1 V IOUT = -50 mA *VIN = VIL or VIH IOH IOUT = 50 mA *VIN = VIL or VIH IOL VI = VCC, GND VI = VCC - 2.1 V VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND VOLD = 1.65 V Max VOHD = 3.85 V Min VIN = VCC or GND 24 mA 24 mA -24 mA -24 mA
Symbol VIH
Parameter Minimum High Level Input Voltage
VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 5.0
VIL
Maximum Low Level Input Voltage
VOH
Minimum High Level Output Voltage
VOL
Maximum Low Level Output Voltage
4.5 5.5 4.5 5.5
IIN DICCT IOZ
Maximum Input Leakage Current Additional Max. ICC/Input Maximum 3-State Current
5.5 5.5 5.5
IOLD IOHD ICC
Minimum Dynamic Output Current Maximum Quiescent Supply Current
5.5 5.5 5.5 8.0
75 -75 80
mA mA mA
*All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS tr = tf = 3.0 ns (For Figures and Waveforms, See Figures 4, 5, and 6.)
Symbol fmax tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Maximum Clock Frequency Propagation Delay Propagation Delay Output Enable Time Output Enable Time Output Disable Time Output Disable Time CP to Qn CP to Qn VCC* (V) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 TA = +25C CL = 50 pF Min 85 2.0 1.5 1.5 1.5 1.5 1.5 Typ - - - - - - - Max - 10.5 9.5 9.0 8.5 10.5 8.0 TA = -40C to +85C CL = 50 pF Min 75 1.5 1.5 1.5 1.0 1.5 1.0 Max - 11.5 10.5 9.5 9.5 11.5 8.5 MHz ns ns ns ns ns ns Unit
*Voltage Range 5.0 V is 5.0 V 0.5 V
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MC74ACT564
AC OPERATING REQUIREMENTS
Symbol ts th tw Parameter Setup Time, HIGH or LOW Hold Time, HIGH or LOW CP Pulse Width Dn to CP Dn to CP HIGH or LOW VCC* (V) Typ 5.0 5.0 5.0 - - - 2.5 1.0 3.0 TA = +25C CL = 50 pF TA = -40C to +85C CL = 50 pF Guaranteed Minimum 3.0 1.0 3.5 ns ns ns Unit
*Voltage Range 3.3 V is 3.3 V 0.3 V. *Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol CIN CPD Input Capacitance Power Dissipation Capacitance Parameter Value Typ 4.5 50 Unit pF pF Test Conditions VCC = 5.0 V VCC = 5.0 V
ORDERING INFORMATION
Device MC74ACT564N MC74ACT564NG MC74ACT564DWR2 MC74ACT564DWR2G Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) 1000 / Tape & Reel 18 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP-20
SOIC-20W
20 20 MC74ACT564N AWLYYWWG 1 1 ACT564 AWLYYWWG
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
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MC74ACT564
SWITCHING WAVEFORMS
tr CP 50% tw 1/fmax tPLH Q 50%
tf 3.0 V 3.0 V GND OE 50% ts tPHL CP th 3.0 V 50% GND
Figure 4.
Figure 5.
VALID 3.0 V DATA 50% GND tsu CP th VCC 50% GND
Figure 6.
450 W INPUT OUTPUT DEVICE UNDER TEST 50 W SCOPE TEST POINT CL*
*Includes all probe and jig capacitance
Figure 7. Test Circuit
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MC74ACT564
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
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MC74ACT564
PACKAGE DIMENSIONS
SOIC-20W DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC74ACT564/D

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